A MOSFET has a gate region for controlling a flow of charge between a source and drain of the FET in accordance with the gate to source voltage of the FET. When a voltage is applied to the gate of a MOSFET transistor, hereinafter FET, the voltage induces first a depletion region within semiconductor material beneath a gate oxide region and then finally a channel of an appropriate carrier for allowing a flow of charge between the drain and the source of the FET.
For a FET having trench isolation regions surrounding an active region thereof, gate metallization extends over an oxide of the isolation region on a first side of the gate and overhangs the gate on an opposite side by a slight amount. The portions of the gate metallization that extend over the isolation regions create residual fields within the oxide of the trench isolation regions. The residual fields are directed toward walls of the semiconductor substrate associated with the active region of the FET and to the substrate floors of the trench isolation regions. These fields, if of sufficient magnitude, create carrier channels in the walls of the active region of the semiconductor substrate and in the substrate floors beneath the isolation regions for allowing parasitic leakage currents to flow in the walls of the active region and in the floor beneath the isolation regions in parallel with the current flowing in the main channel on top of the active region. What is desired, therefore, is a way of controlling the parasitic voltage threshold associated with generating these parasitic leakage currents.
DISCLOSURE OF INVENTION
It is an object of the present invention to provide an improved MOSFET.
It is another object of the present invention to provide an improved MOSFET having a controlled parasitic voltage threshold.
It is another object of the present invention to provide a MOSFET wherein the parasitic voltage threshold is greater than the main voltage threshold of the MOSFET.
In furtherance of these objectives, the present invention provides a trench isolated FET having a wiring layer coupled to a gate active area of the FET. Metallurgy of a predetermined work function relative the work function of the wiring layer resides intermediate the wiring layer and a thick oxide of the trench regions.
In accordance with another aspect of the present invention, the FET has been heated such that the metallurgy and polysilicon of the wiring layer react to form a silicide.
In accordance with another embodiment of the present invention, a method is provided for forming a trench isolated FET transistor. A semiconductor substrate has a FET active region isolated by trench oxide boundaries, and covered with an oxide and a nitrite pad. A layer of metallurgy of predetermined work function is deposited over the substrate including the nitride pad and the shallow trench oxide boundaries. The deposited metallurgy is then planarized by a Chem- Mechanical polish until the nitride pad is exposed. Thereafter, the nitride pad is removed leaving a hole in the deposited metallurgy exposing the oxide at the active region of the FET. The exposed oxide is then removed exposing the active region of the FET. An oxide film is then re-grown over the exposed active region of the FET. Thereafter polysilicon is deposited over the metallurgy and the oxide film as exposed through the hole of the metallurgy. The polysilicon is then patterned in accordance with a desired gate wiring pattern for providing a gate wiring layer including a gate portion of the active region of the FET. The metallurgy is then etched using the patterned polysilicon as an etching mask, thus leaving metallurgy intermediate the gate wiring layer for regions over the oxide of the trenches.
In accordance with one aspect of this embodiment, another step of heating is provided so that the metallurgy interacts with the polysilicon gate wiring layer to form a silicide.
In accordance with another aspect of the present invention, spacers are formed at the sides of the nitride pad before depositing the layer of metallurgy so as to prevent the metallurgy from contacting the active region of the FET.